The present invention relates to the verification of software tools used in the design of integrated circuits, and more particularly to the verification of logic synthesizers and the generation of test vectors for the verification.
In the past, simple logic circuits could be designed by hand. That is, circuit designers could place logic functions such as OR gate and flip-flops on an integrated circuit and realize a desired function. But modern circuits are often made up of several thousand logic functions or gates. For example, a typical circuit may include 40 thousand look-up tables or 100 thousand gates. Accordingly, more powerful ways of representing logic functions have been developed. Among these are VHDL (VHSIC hardware description language, VHSIC is very high speed integrated circuit) or Verilog modeling.
VHDL or Verilog are software methods of modeling complicated logic functions by comparatively simple equations. These models are provided to a synthesizer, which ideally implements the equations in a minimum number of gates to generate a netlist. This netlist may then be used to make an integrated circuit product.
A synthesizer may be thought of as a collection of algorithms used to convert VHDL or Verilog models to a logical netlist. Often, one or more of these algorithms are updated or modified. When this happens, there is a concern about the accuracy of the updated synthesizer. This concern is exacerbated since the synthesizer is disigned and used by two separate parties, that is, the synthesizer is typically provided by a vendor, while it is used by customer of the vendor.
Also, difficulties arise when verifying the accuracy of a synthesizer. Minor software errors may lead to minor errors in the netlist that may be very difficult to find. The presence of an error in the synthesizer software does not mean that every VHDL or Verilog model is incorrectly netlisted. Also, once a particular netlist has been generated, it is often very time consuming to test the functionality of each and every node of the circuit, thus errors may pass unnoticed.
Thus, what is needed is a thorough method of testing logic synthesizers. This method should provide a high probability of catching errors introduced by modifications and improvements made to synthesizer algorithms.